Variable stop generation for transmitter

ABSTRACT

A transmitter for a telegraph receiver in which the bit rate is determined by a high-frequency oscillator and a binary counter frequency divider. The binary counter is reset to an initial condition at the beginning of the transmission of the stop or idle signal after transmission of all of the data bits of a given character. The counter is reset in order to count an initial count of less than its full capability, and the reset of the counter at the end of transmission of a character is delayed for a time equal to the duration of one-half of a data bit. This produces a stop-signal-time that can be controlled from one-half bit in duration, up to 1 1/2 bits in duration, depending upon the initial reset condition of the counter.

nited States Patent Primary Examiner-Kathleen H. Claify Assistant Examiner-David L. Stewart Attameys.l. l4. Landis and R. P. Miller ABSTRACT: A transmitter for a telegraph receiver in which the bit rate is determined by a high-frequency oscillator and a binary counter frequency divider. The binary counter is reset to an initial condition at the beginning of the transmission of the stop or idle signal after transmission of all of the data bits of a given character. The counter is reset in order to count an initial count of less than its full capability, and the reset of the counter at the end of transmission of a character is delayed for a time equal to the duration of one-half of a data bit. This produces a stop-signal-time that can be controlled from onehalf bit in duration, up to 1%; bits in duration, depending upon the initial reset condition of the counter.

PATENTEB JAII 4 B72 ATTORNEY 1 VARIABLE STOP GENERATION FOR TRANSMITTER FIELD OF THE INVENTION This invention relates to telegraph transmission and more particularly to the operation of a telegraph transmitter capable of transmitting a code combination having a stop or idle period that can be varied.

BACKGROUND OF THE INVENTION There are prior telegraph transmitting systems in which transmission can be controlled in such a way as to provide a long or short stop or idle interval between characters; however, this is usually accomplished only by delaying the initiation of the next machine cycle of the telegraph transmitter by a predetermined amount in order to extend the previous cycle.

There are prior telegraph transmitting systems in which the bit rate is determined by a high-frequency, free-running oscillator and a binary counter frequently divider which is reset at the beginning of each character cycle.

It is an object of the present invention to control the stop or idle interval between adjacent character code combinations.

It is another object of the present invention to control the reset of a bit timing mechanism.

SUMMARY OF THE INVENTION The objects of the present invention are achieved by restarting a bit time generator a predetermined delay interval after the initiation of the stop or idle signal and resetting this bit timer at a nonzero condition, thereby generating a stop or idle signal that is the sum of the delay plus the remainder of the initial bit time signal.

BRIEF DESCRIPTION OF THE DRAWING The accompanying drawing shows a schematic block diagram of a transmitting distributor system according to the present invention.

DETAILED DESCRIPTION Referring now to the drawing, a free-running oscillator 10 provides a time base for the entire logic system. The output of the oscillator 10 is delivered to a binary counter 12 which comprises nine bistable multivibrators (or flip-flops) of the type disclosed in U.S. Pat. No. 3,322,896 granted to F. D. Biggam on May 30, 1967.

The bistable multivibrators used in this circuit and described in the Biggam patent have two conjugate outputs called the l output and the output. Therefore, when a given multivibrator is in the binary l state, it delivers a binary l signal from its 1 output and a binary 0" signal from its 0 output. When the bistable multivibrator is in the 0 state, it delivers a 0 signal from its l output and a l signal from its 0" output.

The inputs to such a bistable multivibrator are of two types:

a. priming inputs called P1 and P0 which, upon receipt of a l signal, prime or condition the bistable multivibrator to change to its 1 state or 0 state, as indicated, upon receipt of a trigger signal; and

b. trigger or set inputs called S1 and S0, which upon receipt of a signal transition from the 0 state to the 1" state (called a set signal), in conjunction with prior receipt of a l signal at its associated priming input, cause the bistable multivibrator to assume the state indicated.

An SIA input is also provided. This latter trigger input is always primed or conditioned to set the bistable multivibrator to the 1 "state upon receipt of a set signal. I

Operating at a substantially higher frequency than the bit rate at which information is to be transmitted, the set signals issuing from the oscillator 10 are supplied to the nine-stage binary counter I2 operating as a frequency divider. Therefore, only one set signal is available at the output of the counter I2 for each 5l2 set signals delivered at its input. When a stop pulse having the same length as the information pulses is desired, the output from each of the individual counter stages is taken from its l output and is supplied to the trigger or set input of the next succeeding stage. Each stage of the counter 12 is operated as a complementary bistable multivibrator so that a change in state of the bistable multivibrator occurs as each input set signal is received by the bistable multivibrator. If the counter is initially reset so that all of the stages are in the l state (zero count), then 512 set signals from the oscillator 10 are required before the first output set signal is obtained from the last stage I8 of the counter I2. The time interval for this to occur is the desired bit rate of the information to be transmitted. The output of the oscillator 10 is also delivered to the set input of a reset bistable multivibrator M which controls the reset of the binary counter I2.

A shift register I6 comprises eight bistable multivibrators of the same general type used in the binary counter I2. The l output of the last stage I8 of the binary counter I2 is delivered to the trigger or set inputs of all eight stages of the shift register I6, to advance the signals contained therein by one stage for each set signal obtained from the l of the last stage I8 of the binary counter I2.

Shortly after the time that the counter I2 is reset, information from a suitable source, such as a tape reader, is transferred into and stored in parallel in five stages of the shift re gister I6 by the application of a data sample pulse supplied to the inputs of a plurality of AND-gates 20. Any level of the input signal which is a mark (binary l") enables the data sample pulse to be passed by the respective AND-gate 20 to the SIA set input of the corresponding stage of the shift register I6, thereby setting that shift register stage to the l state. At the same time that the data sample pulse is applied to the AND-gates 20, a pulse also is applied directly to the SIA set input of the first (leftmost) stage of the shift register, caus ing this stage also to be set to the 1 state whenever a data sample pulse occurs.

Each set signal from the 1" output of the last stage I8 causes the information in each stage of shift register I6 to be shifted one stage to the right (as shown in the drawing). The information in the last (rightmost) stage of the shift register I6 is sent via an OR-gate 21 to a data output terminal. At the same time, the shift register 16 is being cleared to the 0 state one stage at a time by the application of successive shift pulses and as a result of the input 22. Logical l signals are steadily applied to the P0 (Prime O) input of the leftmost bistable multivibrator or stage of the shift register 16. Therefore, whenever a trigger pulse (0-tol transition) is sent to the shift register 16 by the last stage 18 of the binary counter I2, the leftmost stage of the shift register 16 is set to the 0 state. The 0" state in the leftmost stage is advanced to the right with each succeeding trigger pulse. When the marking stop signal ("1" state), originally stored in the leftmost stage of the shift register, is shifted into the final (rightmost) output stage of the shift register, all of the remain ing stages are in the 0" state, causing their 0" outputs to issue 1" -state signals. These 1" signals are sensed by a sensing AND-gate 24, which then issues a 1 signal to the ORgate 21 to assure that the data output terminal will be held in the marking or l state for the duration of this signal.

ONE-UNIT STOP l ")A||l;signal to the PI input of the reset bistable multivibrator I4. If this circuit is connected so as to operate with a one-unit stop pulse, the AND-gate 28 provides this l state signal to the reset bistable multivibrator M priming as soon as an output is obtained from the AND-gate 24-, provided, of course, that a control on (1 state) signal is also present on the control input 30 of the control AND-gate 28. The next set signal obtained from the oscillator 10 following the application of the priming (1" state) signal to the PI input of the bistable multivibrator M causes this bistable multivibrator I4 to be set to the l state. The set signal thus issuing from the "1 output of the reset bistable multivibrator 14 is delivered to the SlA inputs of the binary counter 12, thereby resetting the counter 12 to its zero or initial count in the manner described previously. The set signal obtained from the 1" output of the bistable multivibrator 14 also energizes a delay circuit 32 subsequently to provide the data-sample set signal to the AND-gates 20, as described previously.

in addition, the l output of the bistable multivibrator 14 is connected to its own P priming input. Therefore, after it is set to the 1 state, the next pulse obtained from the oscillator immediately resets the bistable multivibrator 14 to the 0 state. The cycle of operation is then repeated with the length of the stop pulse obtained from the output stage of the shift register 16 being substantially equal to the length of the information pulses, since the counter 12 is reset to its zero count as soon as the marking stop pulse is shifted into the final stage of the shift register 16.

1.42-UNlT STOP The following changes are made in the circuit in order to provide for stop pulses of different durations, from one-half unit to 1 units. Specifically, if a 1.42 unit duration is desired, two changes in the above-described cycle of operation are made. First, the fourth and sixth stages of the counter 12 are connected to provide the output to the next succeeding stages from the 0 outputs of these two stages (for example by using two switches 26 and 27). Then, when the counter 12 is reset, it effectively is reset to store a count of 40 rather than a count of zero. If it were not possible to change the connection between the stages in this manner, the fourth and sixth stages could be reset to the 0" state and all the other stages could be reset to the l state, with the interconnections between the stages of the counter remaining the same as those used for the one-unit stop-pulse code described previously. Since the counter 12 is set to a count of 40, only 472 set signals from the oscillator 10 are necessary to provide the first output set signal from the l of the last stage 18 of the binary counter 12. All succeeding output set signals from the last stage 18 still require 512 set signals from the oscillator 10. Therefore, only the first set signal from the last stage 18 is of shorter duration than the remaining set signals applied to the register 16. This would cause the duration of the stop pulse of the transmitted telegraph signal to be approximately 0.92 as long as the stop pulse that would be obtained if the counter 12 were completely reset to zero.

In order to cause the stop pulses to be 1.42 times as long as the unit informationor data pulses of the telegraph signal, it is necessary to add another one-half bit delay to this stop pulse. This is accomplished by closing a switch 34, so that an inhibit (0 state) signal from the 0" output of the last stage 18 is present at an input of the AND-gate 28 at the time that a 1 state signal is obtained from the AND-gate 24. When the switch 34 is open, the AND-gate 28 reacts as though it had only two inputs. This inhibit signal lasts until the last stage 18 of the counter 12 is shifted back to the 0 state, at which time the 0" output of the last stage 18 delivers a l signal to the AND-gate 28. This occurs exactly one-half of a unit pulse interval after the last stage 18 of the counter 12 reverted to the 1 state to generate the last set signal for the shift register 16. As soon as this inhibit signal is removed from the AND-gate 28, the l state priming signal from the AND-gate 28 to the Pl input of the reset bistable multivibrator l4 permits the next set signal from the oscillator 10 to set the reset bistable multivibrator 14 to the 1" state, causing the counter 12 to be reset and causing information to be shifted into the register 16.

In summary, the one-half unit delay obtained by closing the switch 34 is added onto the end of the character just transmitted, causing the mark hold signal obtained from the AND- gate 24 to force the output of the register 16 to remain in a marking or stop condition. Then the reset bistable multivibrator 14 18 set to the l state, resetting the counter 12, which 1.5-UN1T STOP it should be apparent that if it is desirable to have a stop pulse of 1.5 unit length, the counter 12 could be operated in the same manner as used for a one-unit stop pulse, but with the switch 34 being closed to add the additional one-half unit. In addition, if stop pulses of different lengths from 0.5 units up to 1.5 units are desired, they can be obtained by resetting the counter 12 to any desired count, in order to vary the length of time required before the first set signal is obtained from the counter 12. Stop pulses less than 0.5 units can be obtained by opening the switch 34 and setting the binary counter to any initial count greater than zero.

What is claimed is:

l. A method of generating a signal comprising a predetermined number of intelligence pulses plus a stop pulse having a duration greater than the duration of the intelligence pulses which comprises:

presetting a multistage frequency divider with a stored count greater than 0" and having set 1 and set 0 outputs;

storing intelligence signal pulses in a multistage shift register; applying first set signals to drive the frequency divider to produce second set signals in the last stage of the frequency divider and applying said second set signal to successively shift the stored intelligence signal inputs onto a transmission line; generating a reset priming signal upon shifting of the intelligence signals onto the transmission line while impressing a first portion of a stop signal on the transmission line;

producing an inhibit signal from the 0 output of the frequency divider to block the priming signal until the 0 output shifts to the l state; and

applying the unblocked priming signal to reset the frequency divider to an initial state while holding the stop signal condition on the transmission line until another second set signal is produced in the last stage of the frequency divider. 2. A method of driving a multistage resettable counter having a last stage with set 0 and set l outputs so that the output pulses produced by transitions at the set 1" output comprise a series of first pulses of a first duration;

presetting certain stages of the counter to store an initial count to produce an initial set 0 to set l pulse at the set l output at the end of a counting sequence of shorter duration than the time required to produce subsequent set 0" to set 1 pulses; applying constant frequency pulses to drive the counter to produce transitions at the set 0" and set l "outputs;

generating a reset priming signal in response to a first followed by a predetermined number of pulses at the set l output;

applying the set 0 state of the set 0" output to inhibit the priming signal;

inhibiting the priming signal with the set 0" output until said set 0" output switches to set 1 state; generating a reset signal from the uninhibited signal; and

applying the reset signal to restore the counter to the initial condition with the stored count.

priming 

1. A method of generating a signal comprising a predetermined number of intelligence pulses plus a stop pulse having a duration greater than the duration of the intelligeNce pulses which comprises: presetting a multistage frequency divider with a stored count greater than ''''0'''' and having set ''''1'''' and set ''''0'''' outputs; storing intelligence signal pulses in a multistage shift register; applying first set signals to drive the frequency divider to produce second set signals in the last stage of the frequency divider and applying said second set signal to successively shift the stored intelligence signal inputs onto a transmission line; generating a reset priming signal upon shifting of the intelligence signals onto the transmission line while impressing a first portion of a stop signal on the transmission line; producing an inhibit signal from the ''''0'''' output of the frequency divider to block the priming signal until the ''''0'''' output shifts to the ''''1'''' state; and applying the unblocked priming signal to reset the frequency divider to an initial state while holding the stop signal condition on the transmission line until another second set signal is produced in the last stage of the frequency divider.
 2. A method of driving a multistage resettable counter having a last stage with set ''''0'''' and set ''''1'''' outputs so that the output pulses produced by transitions at the set ''''1'''' output comprise a series of first pulses of a first duration; presetting certain stages of the counter to store an initial count to produce an initial set ''''0'''' to set ''''1'''' pulse at the set ''''1'''' output at the end of a counting sequence of shorter duration than the time required to produce subsequent set ''''0'''' to set ''''1'''' pulses; applying constant frequency pulses to drive the counter to produce transitions at the set ''''0'''' and set ''''1'''' outputs; generating a reset priming signal in response to a first followed by a predetermined number of pulses at the set ''''1'''' output; applying the set ''''0'''' state of the set ''''0'''' output to inhibit the priming signal; inhibiting the priming signal with the set ''''0'''' output until said set ''''0'''' output switches to set ''''1'''' state; generating a reset signal from the uninhibited priming signal; and applying the reset signal to restore the counter to the initial condition with the stored count. 